1. Field of Invention
The present invention is related to semiconductor memory and more specifically to chips integrated with different types of memory that preferably use programmable interfaces.
2. Description of Related Art
In the past 20 years, the cell structure, program and erase schemes and manufacturing process for NAND and NOR logic circuits have been incompatible preventing both products from being integrated into one chip. Normally, NAND logic cost is much cheaper than NOR logic, which is because the conventional NAND cell size is the smaller with 4λ2 to store two SLC (single level cell) binary data, where λ is the minimum feature size of the lithography used. The highest NAND density is 64 Gb per chip with a MLC (multi-level cell) storage by using a 30 nm technology node. The conventional ETOX-based NOR cell has a cell size that is approximately 12-16λ2 and is getting more and more difficulty to scale down below 45 nm. Until recently, the highest density for a NOR flash sample is 1 Gb made from a 45 nm process, which is not in the mode of economic production.
Now, a novel SRAM, EEPROM, NAND and NAND-based NOR hybrid memory solution with multiple interfaces, multiple IO's and a fixed number of pins for all densities are possible, which will be disclosed herein in accordance with the spirit of the present invention. Besides the great advantage to achieve the high memory density, the present invention also provides a unique sequence to enter into different interface protocol.